Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

For Loop

A sequential statement used to execute a set of sequential statements repeatedly, with the loop parameter taking each of the values in the given Range from left to right.

Syntax

  [LoopLabel:] for ParameterName in Range loop
    SequentialStatements...
  end loop [LoopLabel];
    

Where

See Sequential Statement

Rules

The loop parameter is implicitly declared by the loop statement itself, and only exists inside the loop. The loop parameter is a constant (i.e. cannot be assigned).

Synthesis

Synthesis make multiple copies of the logic implied by the statements inside the loop. Only synthesizable if the Range is static .

Example

  type Opcode is (Idle, Start, Stop, Clear);
  ...
  for I in 0 to 7 loop
    V := V xor A(I);
    for J in Opcode loop
      S <= J;
      wait for 10 NS;
    end loop;
  end loop;
    

See Also

While Loop, Loop, Exit, Next, Range